The present invention relates to methods and apparatus for evaluating semiconductor devices, and particularly to a method for evaluating the thickness and dielectric breakdown lifetime of an insulating film in a semiconductor element in which a multilayer insulating film as a stack of two or more insulating films is used as a gate insulating film, a capacitive insulating film or an interlayer insulating film, and to an evaluation apparatus for the method.
With recent enhancement of the integration degree, functions and speed of semiconductor integrated circuit devices, the thicknesses of gate insulating films have decreased, so that previously-used silicon dioxide films (SiO2 films) have become insufficient to satisfy specifications such as a standard for the amount of leakage current. In view of this, gate insulating films using new high-κ materials such as hafnium-based materials (e.g., HfOx, HfSiOx, HfAlOx, and HfOxNy) are proposed.
These high-κ materials are expected to be used not only for gate insulating films but also for capacitive insulating films in memories, e.g., an interlayer insulating film between a control gate electrode and a floating gate electrode in a flash memory, or tunnel insulating films, for example.
For such insulating films, a multilayer structure of two or more layers including a high-κ film and either a silicon dioxide film (a SiO2 film) or a silicon nitride film (a Si3N4 film) is generally adopted.
In these circumstances, methods for accurately evaluating a physical thickness of each layer in an insulating film with a multilayer structure have been required. In addition, methods for accurately evaluating the reliability of a gate insulating film with such a multilayer structure, i.e., for accurately predicting the dielectric breakdown lifetime, have also been needed.
As a conventional method for evaluating the physical thickness of each layer in an insulating film having a multilayer structure, cross-section transmission electron microscope (TEM) observation for evaluating the cross-sectional structure and thickness of the insulating film by using a TEM has been adopted in most cases. To accurately predict a dielectric breakdown lifetime, it is inevitable to accurately evaluate the dependence of the lifetime on a stress voltage. In conventional techniques, a dielectric breakdown lifetime is predicted by performing a large number of measurements by using samples to obtain the time required for dielectric breakdown of gate insulating films to occur in actual operation with application of various stress voltages to the samples, i.e., performing a large number of lifetime measurements, and statistically processing results of these measurements (see, for example, M. Koyama et al., International Electron Devices Meeting (IEDM), 2004, pp. 931 to 934).